In the past four decades, the integrated circuit technology is continually developed in accordance with Moore's law, the critical dimension is scaling, the integrated level is continually improving, and the function becomes more and more powerful. Nowadays, the critical dimension of metal oxide semiconductor field effect transistors (MOSFET) comes into sub 50 nm. However, with the scaling in critical dimension, the use of traditional gate stacks formed with silicon oxide gate dielectrics/polysilicon would result in an exponential abrupt rise in leakage current at the gate dielectrics, the depletion effect of polysilicon becomes increasingly grave, and the resistance of the polysilicon gate also increases accordingly. To overcome the abovementioned problems, the industry begins to use the novel gate stack structure, which is formed by high k gate dielectrics and metal gate electrode, to replace the traditional gate stack. With a same equivalent oxide thickness, the high k gate dielectrics have a greater physical thickness such that it is able to effectively reduce the leakage current at the gate dielectrics; besides, the metal gate electrode is able to fundamentally get rid of polysilicon depletion effect.
In order to obtain an appropriate threshold voltage, the work function of the metal gate material for pMOSFET is usually required to be in proximity of 5.2 eV. However, the single element metal material with such a high work function has very stable chemical properties, and thus is hard to etch and also is very expensive, for example, platinum, gold, etc. Therefore, it is not practical to tune the work function of a p-type device with such kind of metal materials.
Accordingly, there is a need to propose a novel p-type semiconductor device and a method for manufacturing the same, so as to effectively tune the work function of pMOSFET and to improve the performance of the devices.